setenv SIM_WORKING_FOLDER .
set newDesign 0
if {![file exists "E:/git/oschina/step_mxo2/labs/sim/lab_pwmpulse/lab_pwmpulse.adf"]} { 
	design create lab_pwmpulse "E:/git/oschina/step_mxo2/labs/sim"
  set newDesign 1
}
design open "E:/git/oschina/step_mxo2/labs/sim/lab_pwmpulse"
cd "E:/git/oschina/step_mxo2/labs/sim"
designverincludedir -clear
designverlibrarysim -PL -clear
designverlibrarysim -L -clear
designverlibrarysim -PL pmi_work
designverlibrarysim ovi_machxo2
designverdefinemacro -clear
if {$newDesign == 0} { 
  removefile -Y -D *
}
addfile "E:/git/oschina/step_mxo2/labs/src/pwmpulse.v"
addfile "E:/git/oschina/step_mxo2/labs/src/pwmpulse_tb.v"
vlib "E:/git/oschina/step_mxo2/labs/sim/lab_pwmpulse/work"
set worklib work
adel -all
vlog -dbg -work work "E:/git/oschina/step_mxo2/labs/src/pwmpulse.v"
vlog -dbg -work work "E:/git/oschina/step_mxo2/labs/src/pwmpulse_tb.v"
module pwmpulse_tb
vsim  +access +r pwmpulse_tb   -PL pmi_work -L ovi_machxo2
add wave *
run 1000ns
